RENEW Project Documentation

Version 1.0

Reconfigurable Ecosystem for Next-generation End-to-end Wireless


Hardware Quick Start

Iris SDR

Faros(R) massive MIMO system is made up of Iris software-defined radio devices. Each Iris device includes an LMS7002M software-defined transceiver chip from Lime Microsystems. It supports 2 TX/RX transceiver channels, can be tuned from 50 MHz up to 3800 MHz, and supports up to 56 MHz of instantaneous bandwidth (complex sampling rate). For more information on LMS7002M transceiver, see here. Iris also has a Xilinx Zynq 7z030 SoC processing element. It includes a dual-core ARM processor as well as FPGA fabric. For more information on this chipset and its available resources, see here. The FPGA fabric is connected to the LMS7002M chip through high-speed lines to send and receive digital baseband samples. It also control the chip through a SPI bus for various control settings such as frequency, gains, sample rate, etc.

Note: Currently streaming a maximum sampling rate of 40 MHz is supported on Iris.

Each Iris device is equipped with a front-end module. Through a standardized interface, multiple types of front-end modules can be used interchangably on an Iris. Currently three type of front-end modules exist to use with Iris: DEV, dual-band BRS/CBRS, and UHF front-ends, all commerically available from Skylark Wireless. The image below show an Iris with a DEV front-end. DEV front-ends do no include amplifiers or filters and simply forward LMS7002M’s output to RF antennas. The other two types, namely BRS/CBRS and UHF front-ends are designed to work on the respective bands, i.e. 2.5/ 3.5 GHz for the BRS/CBRS and 470-700 MHz for the UHF.

Each Iris in the chain receives a reference clock from upstream, performs jitter-cleaning through its clock buffer and forwards the clock downstream to the next Iris device through the interconnect interface (see image below). With this design, the entire array remains phase-locked for coherent MIMO operation. Moreover, through a few FPGA GPIO lines passed through the same interconnects, a time synchronization mechanism is built into the FPGAs where each board can synchronously set its time reference with the rest of the chain. Additionally, data flows through the same interconnects (enabled by GTX transceivers in the FPGAs) and distributed along the chain to/from FPGAs on each Iris with a maximum speeds of 12.8 Gbps. The entire chain is also powered up through 48V power rails passing through the same interface.

In particular, up to 10 Iris devices are daisy-chained to form a coherent antenna array. The below image shows a daisy chain of 9 Iris devices as well as an individual Iris on the right side. The individual Iris is powered by Power-Over-Ethernet (PoE) whereas the Iris chain is powered through a breakout board seen on the left side.

Faros System

Up to a chain of 8 Iris devices are packaged in an enclosure to form a radio head (RH). At the head of the Iris chain, there is a so-called SFP board which breaks out the data lines from the chain to SFP+ modules. This way multiple RHs can be daisy-chained together. Also up to 6 RHs can be directly connected through fiber links to a central hub module. The hub provides data connectivity, clock reference and time synchronization all through the same fiber links to all RHs, thereby making the entire system phase-coherent. The figure below shows a rendering of the entire massive MIMO system with multiple RHs connected to the central hub module on its right side. The image on the left side shows inside of an RH where 4 Irises are daisy-chained together. Note, this configuration is for 2.5GHz operation where a half-wavelength antenna spacing for this band is observed. Since each Iris has a width equal to the half-wavelegth in 3.5GHz band, 8 Irises can be packaged in one RH, resulting in 16 anntena per RH. For both BRS and CBRS configurations, antenna are included inside the RH. There is a dual-polarized patch anntenna installed per Iris in the RH.

Iris is an Ethernet/IP-enabled device. This means communicating with Iris happens through a PC’s Ethernet port. Each Iris has an RJ45 Ethernet port. However this port is only useful when no hub is available. In that case, that port can used to get connection to a PC. Note this port can sustain a rate of maximum 1Gbps which limits the sample rate that can be streamed to the PC. In the case of a chain, only one Iris needs to be connected and the entire chain will automatically be connected. In case of a hub, all traffic from/to the chain is routed to/from the hub as ethernet frames. The hub in turn will be connected through its backhaul ethernet ports (Up to 4x 10Gbps links) to any proecssing server.

Triggering and Time Synchronization

Precise time synchronization is essential in massive MIMO and in beamformign in particular. Faros implemenets a native time synchronization mechanism for this purpose. When time synchronized, all radio elements, i.e. Irises, in Faros system will have a synchronized time reference. This ensures synchronized transmission and reception of signals over the air using a shared time value. Time synchronization in Faros becomes slightly more complicated because of the daisy-chain architecture. This is because sending a trigger (time sync) message to all boards does not reach them at the same time, but rather has to go through each Iris to get to the next. This indicates that each Iris’s time reference will have a delay of \Delta with respect to its upstream board. Therefore, there is a need for a correction procedure so that this delay is measured and calibrated out at the time of the trigger signal. We call this procedure “sync delays” procedure as shown in the figure below and is done before sending a trigger signal to all boards (for a synchronized transmission or reception).

The procedure is as the following:

  • A sync delay message is sent from the hub device to the first Iris device of all chains.\
  • Each head of the chain Iris subsequently forwards this message to the downstream device and so on.\
  • Each device, starts a cycle counter upon receiving the sync delays message.\
  • The last device on the chain loops back the message and send it upstream.\
  • Each device measures the number of cycles taken to receive the looped back sync delays message.\
  • The measured number cycles divided by 2, is used to delay the trigger signal on each device whenever received.\

Note that, both sync delays and trigger signal are issues from host software. We will see more details and examples on this in later parts of this documentation.

Iris and Faros Hub bring up

Note: the instructions in this section are for users with local access to Iris and not POWDER users. POWDER users do not need to update any images for any of their experiments. The RENEW team maintains the FAROS system and Iris clients and keep their image up-to-date.

Iris requires a valid SD card in order to function properly. The SD card contains an FPGA image (BOOT.BIN) and a linux kernel file (image.ub).

Once powered on, a RED and GREEN LEDs next to the RJ45 port will turn on. If a valid SD card is inserted into the Iris, the RED LED turns off after about one second and the GREEN LED stays on. That means FPGA is successfully loaded and Iris is booting up.

You can download a working SD image tar file from here. It is always recommended to use the latest image. All images has version number and a date on the tar file name.

Note that, there are two types of valid images for Iris. There is a generic image that has the FPGA GTX transceivers and daisy-chaining functionality enabled by default. There is a more specialized image that disables the daisy-chaining functionality, so an Iris loaded with this image can only be used in standalone mode. This image also features some additional DSP blocks such as correlator block that is used for over-the-air synchronization (more details here). Such image has the keyword “ue” in the tar file name where as the default image does not have that keyword.

Iris can use any micro SD cards with 8GB capacity or more. Simply use a micro SD card reader to attach your SD card to your PC.

  • Flash the Iris devices with the proper image
    • Download the image and unpack [bundle]

    • Unpack the tarball and the one inside

      • Default: bootfiles-iris030_ue-2020.04.0.1-3-c9adc42.tar.gz
      • Client: bootfiles-iris03-2020.04.0.1-3-c9adc42.tar.gz
    • Copy BOOT.BIN and image.ub files to the SD card of you Iris. Alternatively, you can transfer the files over the network with Iris on and discoverable.

    • The IPv6 address of the Iris looks like fe80::3b3b:21ee:fd81:687%2. Default username and password to Iris devices is {sklk, sklk}.

    • In the Iris device

      scp BOOT.BIN image.up sklk@IrisIPAdress:~
      ssh sklk@IrisIPAddress
      sudo mount /boot
      sudo cp BOOT.BIN image.ub /boot
      sudo sync
      sudo umount /boot
      sudo reboot

Similarly, Faros hub needs a valid SD card that is accessible from the link above. It can also be flashed the same way.

Last updated on 15 Jul 2020 / Published on 19 Mar 2019